Regviz

Allwinner /D1H /UART[2] /RXDMA_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RXDMA_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Allwinner/D1H/UART[2]/RXDMA_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disable)enable 0 (Continous)mode 0 (B8)blk_size 0 (SINGLE)ahb_burst_mode 0 (timeout_enable)timeout_enable 0timeout_threshold

mode=Continous, enable=Disable, blk_size=B8, ahb_burst_mode=SINGLE

Description

UART RXDMA Control Register

Fields

enable

0 (Disable): undefined

1 (Enable): undefined
mode

0 (Continous): undefined

1 (Limited): undefined
blk_size

0 (B8): undefined

1 (B16): undefined

2 (B32): undefined

3 (B64): undefined
ahb_burst_mode

Set for AHB port burst supported

0 (SINGLE): undefined

1 (INCR4): undefined

2 (INCR8): undefined

3 (INCR16): undefined
timeout_enable

RXDMA Timeout Enable
timeout_threshold

RXDMA Timeout Threshold

Unit is 1 UART bit time

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data